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參數(shù)資料
| 型號(hào)： | SPM32-CA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | SPMTM (Smart Power Module) |
| 中文描述： | SPMTM（智能功率模塊） |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 428K |
| 代理商： | SPM32-CA |
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2006 Fairchild Semiconductor Corporation
F
April 3, 2006
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN
, IN
, IN
(WL)
, IN
(UH)
, IN
(VH)
and IN
(WH)
should be placed on the SPM pins
and on the both sides of CPU and SPM for the fault output signal, V
FO
, as close as possible.
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) R
C
/R
C
/R
PF
C
PF
coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible to
each of SPM pins.
Fig. 12. Recommended CPU I/O Interface Circuit
Note:
1) It would be recommended that the bootstrap diode, D
BS
, has soft and fast recovery characteristics.
2) The bootstrap resistor (R
BS
) should be 3 times greater than R
E(H)
. The recommended value of R
E(H)
is 5.6
, but it can be increased up to 20
for a slower dv/dt
of high-side.
3) The ceramic capacitor placed between V
CC
-COM should be over 1
μ
F and mounted as close to the pins of the SPM as possible.
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
CPU
COM
5V-Line
1.2nF
0.47nF
1nF
4.7k
4.7k
,
,
IN
(UL)
IN
(VL)
IN
(WL)
,
,
IN
(UH)
IN
(VH)
IN
(WH)
V
FO
100
100
100
1nF
SPM
2k
R
=
R
PL
=
R
=
C
=
C
=
C
=
15V-Line
47uF
0.1uF
470uF
1uF
One-Leg Diagram of
FSAM50SM60A
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
Inverter
Output
P
N
These Values depend on PWM Control Algorithm
D
BS
R
E(H)
R
BS
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