參數(shù)資料
型號: SPE1212S52RG
英文描述: 2-Line ESD Protection Array
中文描述: 2線ESD保護(hù)陣列
文件頁數(shù): 5/7頁
文件大小: 235K
代理商: SPE1212S52RG
APPLICATION NOTE
Device Connection for Protection of Two Data Lines
2006/11/26
Ver.1
Page 5
SPE1212
2-Line ESD Protection Array
SPE1212 is designed to protect up to two data lines. The device is connected as follows:
1.
The TVS protection of two I/O lines is achieved by connecting pins 1 and 2 to the data lines. Pin 3 is connected
to ground. The ground connection should be made directly to the ground plane for best results. The path length
is kept as short as possible to reduce the effects of parasitic inductance.
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the input terminals or connectors to restrict transient coupling.
2. Minimize the path length between the TVS and the protected line.
3. Minimize all conductive loops including power and ground loops.
4. The ESD transient return path to ground should be kept as short as possible.
5. Never run critical signals near board edges.
6. Use ground planes whenever possible.
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