參數(shù)資料
型號(hào): SPC560B50L5C5E0Y
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-144
文件頁(yè)數(shù): 2/74頁(yè)
文件大?。?/td> 971K
代理商: SPC560B50L5C5E0Y
SPC560Bx, SPC560Cx
Device blocks
Doc ID 14619 Rev 4
2.2
Device block summary
Table 3 summarizes the functions of all blocks present in the SPC560Bx and SPC560Cx
series of microcontrollers. Please note that the presence and number of blocks varies by
device and package.
Table 3.
SPC560Bx and SPC560Cx series block summary
Block
Function
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
Analog-to-digital converter (ADC)
Multi-channel, 10-bit analog-to digital-converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed
according to the boot mode of the device
Clock generation module (CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the
eMIOS or from the PIT
Deserial serial peripheral interface
(DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the
device
Inter-integrated circuit (I2C) bus
A two wire bidirectional serial bus that provides a simple and efficient method
of data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINflex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
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