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參數(shù)資料
| 型號(hào)： | SPAKXC16Z1VFV20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, SMT-144 |
| 文件頁數(shù)： | 166/200頁 |
| 文件大?。?/td> | 1383K |
| 代理商： | SPAKXC16Z1VFV20 |
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MOTOROLA
MC68HC16Z1
68
MC68HC16Z1TS/D
can be made. Internal assertion of an interrupt request signal does not affect the logic state of the cor-
responding MCU pin.
External interrupt requests are routed to the CPU16 via the external bus interface and SIM interrupt con-
trol logic — the CPU treats external interrupt requests as though they come from the SIM.
External IRQ[6:1] are active-low level-sensitive inputs. External is an active-low transition-sensitive in-
put — it requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable.IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent
redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is as-
serted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis — to be valid, a request signal must be asserted for at least two consecutive
clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pend-
ing requests are processed at instruction boundaries or when exception processing of higher-priority
exceptions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the
CPU does not recognize the occurrence of the request in any way.
3.7.1 Interrupt Acknowledge and Arbitration
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 de-
tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs
a CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the inter-
rupt source. The mask value also serves two purposes: it is latched into the CCR IP field in order to
mask lower-priority interrupts during exception processing, and it is decoded by modules that have re-
quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to
them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by means of
serial contention between module interrupt arbitration (IARB) field bit values.
Each module that can make an interrupt service request, including the SIM, has an IARB field in its con-
figuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111 (high-
est priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt
exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the
reset IARB value for all other modules is %0000. Initialization software must assign different IARB val-
ues in order to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same nonzero
value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SIM
wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by
a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
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