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參數(shù)資料
| 型號(hào)： | SPAKXC16Z1VFV20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, SMT-144 |
| 文件頁(yè)數(shù)： | 147/200頁(yè) |
| 文件大小： | 1383K |
| 代理商： | SPAKXC16Z1VFV20 |
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MOTOROLA
MC68HC16Z1
50
MC68HC16Z1TS/D
If an external reference signal or an external system clock signal is applied through the EXTAL pin, the
XTAL pin must be left floating. External reference signal frequency must be less than or equal to max-
imum specified reference frequency. External system clock signal frequency must be less than or equal
to maximum specified system clock frequency.
When an external system clock signal is applied (PLL not used), duty cycle of the input is critical, espe-
cially at near maximum operating frequencies. The relationship between clock signal duty cycle and
clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% – percentage variation of external clock input duty cycle
3.4.2 Clock Synthesizer Operation
A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator.
The other phase comparator input is a reference signal, either from the internal oscillator or from an
external source. The comparator generates a control signal proportional to the difference in phase be-
tween its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.
The synthesizer locks when VCO frequency is identical to reference frequency. Lock time is affected by
the filter time constant and by the amount of difference between the two comparator inputs. Whenever
comparator input changes, the synthesizer must re-lock. Lock status is shown by the SLOCK bit in SYN-
CR.
The MC68HC16Z1 does not come out of reset state until the synthesizer locks. Crystal type, character-
istic frequency, and layout of external oscillator circuitry affect lock time.
The low-pass filter requires an external low-leakage capacitor, typically 0.1
F, connected between the
XFC and VDDSYN pins.
VDDSYN is used to power the clock circuits. A separate power source increases MCU noise immunity
and can be used to run the clock when the MCU is powered down. Use a quiet power supply as the
VDDSYN source, since PLL stability depends on the VCO, which uses this supply. Place adequate ex-
ternal bypass capacitors as close as possible to the VDDSYN pin to ensure stable operating frequency.
When the clock synthesizer is used, control register SYNCR determines operating frequency and vari-
ous modes of operation. Because the CPU16 in the MC68HC16Z1 operates only in supervisor mode,
SYNCR can be read or written at any time.
The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting
X doubles clock speed without changing VCO speed. There is no VCO relock delay. The SYNCR W bit
controls a 3-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four.
The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide
by a value of Y
+ 1. When either W or Y value changes, there is a VCO relock delay.
Clock frequency is determined by SYNCR bit settings as follows:
FSYSTEM = FREFERENCE [4(Y + 1)(2
2W + X)]
In order for the device to perform correctly, the clock frequency selected by the W, X, and Y bits must
be within the limits specified for the MCU.
VCO frequency is determined by:
FVCO = FSYSTEM (2 – X)
The reset state of SYNCR ($3F00) produces a modulus-64 count — system frequency is 256 times ref-
erence frequency.
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