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參數(shù)資料
| 型號(hào)： | SPAKXC16Z1MFV20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, SMT-144 |
| 文件頁(yè)數(shù)： | 162/200頁(yè) |
| 文件大小： | 1383K |
| 代理商： | SPAKXC16Z1MFV20 |
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MOTOROLA
MC68HC16Z1
64
MC68HC16Z1TS/D
The bits in this register control the function of each port F pin. Any bit set to one defines the correspond-
ing pin to be an interrupt request input as defined in the register diagram. Any bit cleared to zero defines
the corresponding pin as an I/O pin, controlled by the port F data and data direction registers. The MOD-
CLK signal has no function after reset.
Data bus bit 9 controls the state of this register following reset. If DB9 is set to one during reset, the
register is set to $FF, which denes all port F pins as interrupt request inputs. If DB9 is cleared to zero
during reset, this register is set to $00, dening all port F pins as I/O pins.
3.6 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The
MC68HC16Z1 performs resets with a combination of hardware and software. The system integration
module determines whether a reset is valid, asserts control signals, performs basic system configura-
tion and boot ROM selection based on hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
The reset status register contains a bit for each reset source in the MCU. A bit set to one indicates what
type of reset has occurred. When multiple reset sources occur at the same time, more than one bit in
RSR can be set. The reset status register is updated by the reset control logic when the MCU comes
out of reset. This register can be read at any time. A write has no effect.
EXT — External Reset
Reset was caused by an external signal.
POW — Power-Up Reset
Reset was caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset was caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset was caused by the system protection submodule halt monitor.
LOC — Loss of Clock Reset
Reset was caused by loss of clock submodule frequency reference. This reset can only occur if the
RSTEN bit in the clock submodule is set and the VCO is enabled.
PFPAR — Port F Pin Assignment Register
$YFFA1F
7
6
5
4
3
2
1
0
PFPA7
(IRQ7)
PFPA6
(IRQ6)
PFPA5
(IRQ5)
PFPA4
(IRQ4)
PFPA3
(IRQ3)
PFPA2
(IRQ2)
PFPA1
(IRQ1)
PFPA0
(MODCLK)
RESET:
DB9
RSR — Reset Status Register
$YFFA07
7
6
5
4
3
2
1
0
EXT
POW
SW
HLT
0
LOC
SYS
TST
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| SPAKXCF333CFT20 | 32-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP16 |
| SPAKXCF333MFT20 | 32-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP16 |
| SPAKXCF333VFT20 | 32-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPAKXC301GC100D | 制造商:Motorola Inc 功能描述: |
| SPAKXC301PW100D | 制造商:Motorola Inc 功能描述: |
| SPAKXC309AG100A | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SPAKXC309GC100A | 制造商:Motorola 功能描述:MOTOROLA |
| SPAKXC309VF100A | 功能描述:IC DSP 24BIT 100MHZ 196-MAPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:DSP563xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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