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參數(shù)資料
| 型號： | SPAKXC16Z1MFC16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, SMT-132 |
| 文件頁數(shù)： | 142/200頁 |
| 文件大?。?/td> | 1383K |
| 代理商： | SPAKXC16Z1MFC16 |
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MOTOROLA
MC68HC16Z1
46
MC68HC16Z1TS/D
The module configuration register controls system configuration. It can be read or written at any time,
except for the module mapping (MM) bit, which can be written once and must remain set.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
tinue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
abled, preventing interrupts during software debug.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DB11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor data space or user data space. The
CPU16 in the MC68HC16Z1 operates only in supervisory mode. SUPV has no effect.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IMB address lines ADDR[23:20] follow the logic state of ADDR19 unless externally driven. MM corre-
sponds to IMB ADDR23. If it is cleared, the SIM maps IMB modules into address space $7FF000 –
$7FFFFF, which is inaccessible to the CPU. Modules remain inaccessible until reset occurs. MM can
be written once. Initialization software should set MM to logic level 1.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU16 pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the
CPU16, the SIM IARB field value is used for arbitration between internal and external interrupts of the
same priority. The reset value of IARB for the SIM is %1111 (highest priority), and the reset IARB value
for all other modules is %0000, which prevents SIM interrupts from being discarded during initialization.
SHEN
Action
00
Show cycles disabled, external arbitration enabled
01
Show cycles enabled, external arbitration disabled
10
Show cycles enabled, external arbitration enabled
11
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
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