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參數(shù)資料
| 型號： | SP98608BDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.002 us SETTLING TIME, 8-BIT DAC, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 312K |
| 代理商： | SP98608BDG |
SP98608
2
Dynamic characteristic
(Note 1)
Symbol
Min.
Value
Typ.
Max.
Unit
Conditions
Update rate
Latch setup time
Latch hold time
Settling time full scale
Internal clock delay
Internal time to 10%
FCLK
ts
th
tst
tc
ti
0
450
0.9
2
500
50
MHz
ns
ps
1/2 LSB
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = 25°C; VEE = -5.2V ± 5%; RSET = 240; Input voltage: High = -0.81V, Low = -1.85V
Characteristic
Min.
Value
Typ.
Max.
Unit
Conditions
Supply current IEE
135
154
mA
all inputs at -1.8V
Digital inputs
Input High voltage, VIH
Input Low voltage, VIL
Input High current, IIH
Reference voltage VREF
Reference voltage temp. coeff.
Output current - full scale
Output compliance
Bit size (LSB)
Resolution
-0.96
-1.85
2
38
-1.2
-1.0
158
8
115
-1.280
0
42
166
-0.81
-1.65
200
±80
44
+1.0
175
V
A
V
ppm/
°C
mA
V
A
Bits
standard ECL
10K compatible
all inputs HI
-30
°C to +85°C
RSET 1.3k to 85k
RSET = 130
Tamb = 25°C Note 3
Tamb = 85°C Note 3
current output
RSET = 130
Accuracy
Integral non-linearity
Differential non-linearity
±0.5
LSB
Output dynamic parameters (see Note 1)
Rise time tr
Glitch energy (latched)
Glitch energy (transparent)
Noise output
Power supply rejection ratio (output WRT supply)
45
600
20
140
-90
80
-83
ps
psV
dBm
dB
10 to 90%
mid-point
transition
see Note 2
±0.3V at 20kHz
Multiplying mode - voltage
Multiplying input voltage range
Reference input resistance
Multiplying input bandwidth
Transfer function non-linearity
-2
10
30
0.2
0
1.0
V
k
MHz
dB
-3dB
DC
Multiplying mode - current
Multiplying input voltage range
Reference input resistance
Multiplying input bandwidth
Transfer function non-linearity
1
400
300
1.0
15
3.0
mA
Ohms
MHz
%FS
-3dB
DC
NOTES
1. Dynamic parameters guaranteed but not 100% tested.
2. Noise in any 10kHz band in the range 0.1 to 500MHz, for any digital input.
3. The output positive compliance can be increased beyond +1.0V at the expense of linearity. SEe Fig.4 for circuit conguration.
4. Analog and digital grounds should be connected together at the device pins.
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