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參數(shù)資料
| 型號(hào)： | SP508EF-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 16/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX MULTIPROTOCOL 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 1016-1193 |
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ExarCorporation48720KatoRoad,FremontCA,9453850-668-707www.exar.comSP508_00_02709
Thechargepumpcyclewillcontinueaslong
astheoperationalconditionsfortheinternal
oscillatorarepresent.
SincebothV+andV-areseparatelygener-
atedfromV
CC;inano-loadconditionV
+
and
V-willbesymmetrical.Olderchargepump
approachesthatgenerateV-fromV+willshow
adecreaseinthemagnitudeofV-compared
to V+ due to the inherent inefficiencies in
thedesign.
Theclockrateforthechargepumptypically
operatesat250kHz.Theexternalcapacitors
canbeaslowasFwitha6Vbreakdown
voltagerating.
TERM_OFFFUNCTION
The SP508 contains a TERM_OFF pin
that disables all three receiver input ter-
mination networks regardless of mode.
This allows the device to be used in
monitor mode applications that are typi-
cally found in networking test equipment.
TheTERM_OFFpininternallycontainsa
pull-downdevicewithanimpedanceofover
500k, which will default in a “ON” condition
duringpower-upifV.35receiversareused.
The individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.
LOOPBACkFUNCTION
TheSP508containsaLOOPBACKpinthat
invokesaloopbackpath.Thisloopbackpath
isillustratedinFigure46.LOOPBACKhas
aninternalpull-upresistorthatdefaultsto
normalmodeduringpoweruporifthepinis
left floating. During loopback, the driver out-
putandreceiverinputcharacteristicswillstill
adhere to its appropriate specifications.
DECODERANDD_LATChFUNCTION
The SP508 contains a D_LATCH pin
that latches the data into the D0, D,
and D2 decoder inputs. If tied to a
logic LOW (“0”), the latch is transpar-
ent, allowing the data at the decoder in-
puts to propagate through and program
the SP508 accordingly. If tied to a logic
HIGH(“”),thelatchlocksoutthedataand
preventsthemodefromchanginguntilthis
pinisbroughttoalogicLOW.
Thereareinternalpull-updevicesonD0,
D,andD2,whichallowthedevicetobein
SHUTDOWNmode(“”)uponpowerup.
However,ifthedeviceispowered-upwith
theD_LATCHatalogicHIGH,thedecoder
state of the SP508 will be undefined.
ESDTOLERANCE
TheSP508deviceincorporatesruggedized
ESDcellsonalldriveroutputandreceiver
inputpins.TheESDstructureisimproved
over our previous family for more rugged
applications and environments sensitive
toelectrostaticdischargesandassociated
transients.
CTR1/CTR2EUROPEANCOMPLIANCY
As with all of Exar’s previous multi-
protocol serial transceiver IC’s, the
drivers and receivers have been de-
signed to meet all the requirements to
NET/NET2 and TBR2 in order to meet
CTR/CTR2 compliancy. The SP508 is
alsotestedin-houseatExarandadheres
to all the NET/2 physical layer testing
and the ITU Series V specifications before
shipment. Please note that although the
SP508 , as with its predecessors, ad-
here to CTR/CTR2 compliancy testing,
anycomplexorunusualconfigurationshould
bedouble-checkedtoensureCTR/CTR2
compliance. Consult the factory for de-
tails.
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