• 參數(shù)資料
    型號(hào): SP508EF-L
    廠商: Exar Corporation
    文件頁(yè)數(shù): 14/29頁(yè)
    文件大?。?/td> 0K
    描述: IC TXRX MULTIPROTOCOL 100LQFP
    標(biāo)準(zhǔn)包裝: 90
    類型: 收發(fā)器
    驅(qū)動(dòng)器/接收器數(shù): 8/8
    規(guī)程: 多協(xié)議
    電源電壓: 5V
    安裝類型: 表面貼裝
    封裝/外殼: 100-LQFP
    供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
    包裝: 托盤(pán)
    其它名稱: 1016-1193
    2
    ExarCorporation48720KatoRoad,FremontCA,9453850-668-707www.exar.comSP508_00_02709
    ThefourthtypeofdriversareV.35differential
    drivers.Thereareonlythreeavailableonthe
    SP508fordataandclock(TxD,TxCE,and
    TxCinDCEmode).Thesedriversarecurrent
    sources that drive loop current through
    a differential pair resulting in a 550mV
    differential voltage at the receiver. These
    drivers also incorporate fixed termination
    networksforeachdriverinordertosetthe
    V
    OHandVOLdependingonloadconditions.
    Thisterminationnetworkisbasicallya“Y”
    configuration consisting of two 51 resistors
    connected in series and a 124 resistor
    connected between the two 50 resistors
    andaV35TGNDoutput.Eachofthethree
    drivers and its associated termination will
    haveitsownV35TGNDoutputforgrounding
    convenience. Filtering can be done on
    thesepinstoreducecommonmodenoise
    transmitted over the transmission line by
    connectingacapacitortoground.
    Thedriversalsohaveseparateenablepins
    which simplifies half-duplex configurations
    forsomeapplications,especiallyprogram-
    mableDTE/DCE.Theenablepinswilleither
    enableordisabletheoutputofthedrivers
    according to the appropriate active logic
    illustrated on Figure 45. The enable pins
    haveinternalpull-upandpull-downdevices,
    dependingontheactivepolarityofthere-
    ceiver,thatenablethedriveruponpower-on
    if the enable lines are left floating. During
    disabledconditions,thedriveroutputswill
    beatahighimpedance3-state.
    ThedriverinputsarebothTTLandCMOS
    compatible.Alldriverinputshaveaninternal
    pull-upresistorsothattheoutputwillbeat
    a defined state at logic LOW (“0”). Unused
    driver inputs can be left floating. The inter-
    nalpull-upresistorvalueisapproximately
    500k.
    Receivers
    The SP508 has eight enhanced inde-
    pendent receivers. Control for the mode
    selection is done via a three-bit con-
    trol word that is the same as the driver
    control word. Therefore, the modes for
    thedriversandreceiversareidenticalinthe
    application.
    Like the drivers, the receivers are prear-
    ranged for the specific requirements of
    the synchronous serial interface. As the
    operatingmodeofthereceiversischanged,
    the electrical characteristics will change
    to support the required serial interface
    protocols of the receivers.Table 2 shows
    themodeofeachreceiverinthedifferent
    interface modes that can be selected.
    Therearetwobasictypesofreceivercir-
    cuits—ITU-T-V.28(RS-232)andITU-T-V.,
    (RS-422).
    TheRS-232(V.28)receiverissingle-ended
    andacceptsRS-232signalsfromtheRS-
    232 driver. The RS-232 receiver has an
    operatinginputvoltagerangeof+5Vand
    canreceivesignalsdownsto+3V.Theinput
    sensitivitycomplieswithRS-232andV.28
    at+3V. The input impedance is 3k to 7k
    inaccordancetoRS-232andV.28.The
    receiveroutputproducesaTTL/CMOSsignal
    witha+2.4Vminimumforalogic“”anda
    +0.4Vmaximumforalogic“0”.TheRS-232
    (V.28)protocolusesthesereceiversforall
    data,clockandcontrolsignals.Theyarealso
    usedinV.35modeforcontrollinesignals:
    CTS,DSR,LL,andRL.TheRS-232receiv-
    erscanoperateover20kbps.
    Thesecondtypeofreceiverisadifferential
    type that can be configured internally to
    support ITU-T-V.0 and CCITT-V.35
    depending on its input conditions. This
    receiver has a typical input impedance
    of 10k and a differential threshold of
    less than +200mV, which complies with
    the ITU-T-V.11 (RS-422) specifications.
    V. receivers are used in RS-449/V.36,
    EIA-530,EIA-530AandX.2asCategoryI
    signalsforreceivingclock,data,andsome
    controllinesignalsnotcoveredbyCategory
    IIV.0circuits.ThedifferentialV.trans-
    ceiverhasimprovedarchitecturethatallows
    over20Mbpstransmissionrates.
    Receiversdedicatedfordataandclock(RxD,
    RxC,TxC)incorporateinternaltermination
    forV..Theterminationresistoristypically
    120connectedbetweentheAandBinputs.
    Theterminationisessentialforminimizing
    crosstalk and signal reflection over the
    transmission line .The minimum value is
    guaranteed to exceed 100, thus complying
    with the V.11 and RS-422 specifications.
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