參數資料
型號: SP503EM-L
廠商: Exar Corporation
文件頁數: 28/28頁
文件大?。?/td> 0K
描述: IC TXRX MULTIPROTOCOL 80LQFP
標準包裝: 84
類型: 收發(fā)器
驅動器/接收器數: 7/7
規(guī)程: 多協(xié)議
電源電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-LQFP(14x14)
包裝: 托盤
9
SP503_101_101508
SP503 Multiprotocol Transceiver
Copyright 2008 Exar Corporation
Figure 3. Charge Pump Waveforms
+10V
GND
–10V
C
2
+
C
2
a)
b)
VCC = +5V
–10V
VSS Storage Capacitor
VDD Storage Capacitor
C1
C2
C3
C4
+
++
Figure 2. Charge Pump Phase 2.
and RS-423 drivers. For the RS-232 driver, the
current requirement will be 3.5mA per driver,
and for the RS-423 driver, the worst case current
drain will be 11mA per driver. The external
power supplies should provide a power supply
sequence of : +l0V, then +5V, followed by –l0V.
Drivers
The SP503 has seven (7) independent drivers,
two of which have separate active–low tri–state
controls. If a half-duplex channel is required,
this can be achieved with external connections.
Control for the mode selection is done via a
four–bit control word. The SP503 does not have
a latch; the control word must be externally
latched either high or low to write the appropri-
ate code into the SP503. The drivers are pre-
arranged such that for each mode of operation
the relative position and functionality of the
drivers are set up to accommodate the selected
interface mode. As the mode of the drivers is
changed, the electrical characteristics will change
to support the requirements of clock, data, and
control line signal levels. Table 1 shows a sum-
mary of the electrical characteristics of the driv-
ers in the different interface modes. Unused
driver inputs can be left floating; however, to
ensure a desired state with no input signal, pull–
up resistors to +5V or pull–down resistors to
ground are suggested. Since the driver inputs
are both TTL or CMOS compatible, any value
resistor less than 100k
will suffice.
simultaneously with this, the positive side of
capacitor C
1 is switched to +5V and the negative
side is connected to ground, and the cycle be-
gins again.
Since both V+ and Vare separately generated
from V
CC in a no–load condition, V+ and V
will
be symmetrical. Older charge pump approaches
that generate Vfrom V+ will show a decrease
in the magnitude of Vcompared to V+ due to
the inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be 22F with a 16V breakdown rating.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
Vpins. The value of the external supply volt-
ages must be no greater than ±l0V. The current
drain for the ±10V supplies is used for RS-232,
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