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參數(shù)資料
| 型號(hào)： | SNJ54LVTH16646WD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| 封裝： | CERAMIC, DFP-56 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 398K |
| 代理商： | SNJ54LVTH16646WD |
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SN54LVTH16646, SN74LVTH16646
3.3V ABT 16BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3STATE OUTPUTS
SCBS698G JULY 1997 REVISED MAY 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH16646
SN74LVTH16646
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
MHz
tw
Pulse duration, CLK high or low
3.3
ns
tsu
Setup time,
Data high
1.2
1.5
1.2
1.5
ns
tsu
Setup time,
A or B before CLKAB
↑ or CLKBA↑
Data low
2
2.8
2
2.8
ns
th
Hold time,
Data high
0.5
0
0.5
0
ns
th
Hold time,
A or B after CLKAB
↑ or CLKBA↑
Data low
0.5
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
SN54LVTH16646
SN74LVTH16646
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
fmax
150
MHz
tPLH
CLKBA or
A or B
1.3
4.5
5
1.3
2.8
4.2
4.7
ns
tPHL
CLKBA or
CLKAB
A or B
1.3
4.5
5
1.3
2.8
4.2
4.7
ns
tPLH
A or B
B or A
1
3.6
4.1
1
2.4
3.4
3.9
ns
tPHL
A or B
B or A
1
3.6
4.1
1
2.1
3.4
3.9
ns
tPLH
SBA or SAB
A or B
1
4.7
5.6
1
2.8
4.5
5.4
ns
tPHL
SBA or SAB
A or B
1
4.7
5.6
1
3
4.5
5.4
ns
tPZH
OE
A or B
1
4.5
5.4
1
2.5
4.3
5.2
ns
tPZL
OE
A or B
1
4.5
5.4
1
2.6
4.3
5.2
ns
tPHZ
OE
A or B
2
5.8
6.3
2
4
5.6
6.1
ns
tPLZ
OE
A or B
2
5.6
6.3
2
3.6
5.4
6.1
ns
tPZH
DIR
A or B
1
4.6
5.5
1
3
4.4
5.3
ns
tPZL
DIR
A or B
1
4.6
5.5
1
3
4.4
5.3
ns
tPHZ
DIR
A or B
1.5
6
7.1
1.5
3.9
5.7
6.8
ns
tPLZ
DIR
A or B
1.5
5.5
6
1.5
3.6
5.2
5.7
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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