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參數(shù)資料
| 型號： | SNJ54LV74AJ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 808K |
| 代理商： | SNJ54LV74AJ |
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L AUGUST 1997 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
L
H
H
L
H
LX
XL
H
L
LX
X
H
H
↑
HH
L
H
↑
LL
H
L
X
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
TG
C
TG
C
TG
C
TG
C
PRE
CLK
D
CLR
Q
C
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