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參數(shù)資料
| 型號： | SNJ54AS1008AFK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 門電路 |
| 英文描述： | AS SERIES, QUAD 2-INPUT AND GATE, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 55K |
| 代理商： | SNJ54AS1008AFK |
SN54ALS1008A, SN54AS1008A, SN74ALS1008A, SN74AS1008A
QUADRUPLE 2-INPUT POSITIVE-AND BUFFERS/DRIVERS
SDAS071A – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
1
’ALS1008A is a Buffer Version of ’ALS08
’AS1008A is a Driver Version of ’AS08
’AS1008A Offers High Capacitive Drive
Capability
Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
description
These devices contain four independent 2-input
AND buffers/drivers. They perform the Boolean
functions Y = A
B or Y = A+B in positive logic.
The SN54ALS1008A and SN54AS1008A are
characterized for operation over the full military
temperature range of – 55
°C to 125°C. The
SN74ALS1008A and SN74AS1008A are charac-
terized for operation from 0
°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
Y
H
L
XL
X
L
logic symbol
1
1A
1B
2
2A
4
2B
5
3A
9
3B
10
4A
12
4B
13
3
1Y
2Y
6
3Y
8
4Y
11
&
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
1A
1B
1Y
2Y
2B
2A
3Y
3B
3A
4Y
4B
4A
logic diagram (positive logic)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
SN54ALS1008A, SN54AS1008A ...J PACKAGE
SN74ALS1008A, SN74AS1008A ...D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
SN54ALS1008A, SN54AS1008A . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
3A
4B
2Y
GND
NC
NC – No internal connection
CC
V
3Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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