參數(shù)資料
型號(hào)： SN74SSTVF32852KR
廠商： TEXAS INSTRUMENTS INC
元件分類： 鎖存器
英文描述： SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114
封裝： PLASTIC, BGA-114
文件頁(yè)數(shù)： 8/13頁(yè)
文件大小： 442K
代理商： SN74SSTVF32852KR
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
VDDQ
2.7
V
VDDQ
Output supply voltage
PC1600, PC2100, PC2700
2.3
2.7
V
VDDQ
Output supply voltage
PC3200
2.5
2.7
V
VREF
Reference voltage (VREF =VDDQ/2)
PC1600, PC2100, PC2700
1.15
1.25
1.35
V
VREF
Reference voltage (VREF = VDDQ/2)
PC3200
1.25
1.3
1.35
V
VTT
Termination voltage
VREF–40mV
VREF
VREF+40mV
V
VI
Input voltage
0
VCC
V
VIH
AC high-level input voltage
Data inputs
VREF+310mV
V
VIL
AC low-level input voltage
Data inputs
VREF–310mV
V
VIH
DC high-level input voltage
Data inputs
VREF+150mV
V
VIL
DC low-level input voltage
Data inputs
VREF–150mV
V
VIH
High-level input voltage
RESET
1.7
V
VIL
Low-level input voltage
RESET
0.7
V
VICR
Common-mode input voltage range
CLK, CLK
0.97
1.53
V
VI(PP) Peak-to-peak input voltage
CLK, CLK
360
mV
IOH
High-level output current
–8
mA
IOL
Low-level output current
8
mA
TA
Operating free-air temperature
0
70
_C
NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VIK
II = –18 mA
2.3 V
–1.2
V
VOH
IOH = –100 A
2.3 V to 2.7 V
VDDQ–0.2
V
VOH
IOH = –8 mA
2.3 V
1.95
V
VOL
IOL = 100 A
2.3 V to 2.7 V
0.2
V
VOL
IOL = 8 mA
2.3 V
0.35
V
II
All inputs
VI = VCC or GND
2.7 V
±5
A
ICC
Static standby
RESET = GND
IO =0
27 V
10
A
ICC
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
IO = 0
2.7 V
35
mA
Dynamic operating –
clock only
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
38
A/
MHz
ICCD
Dynamic operating –
per each data input
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
IO = 0
2.5 V
7
A/
clock
MHz/
D input
Data inputs
VI = VREF ± 310 mV
2.8
3.3
3.8
Ci
CLK, CLK
VICR = 1.25 V, VI(PP) = 360mV
2.5 V
2.5
3
3.5
pF
RESET
VI = VCC or GND
3
4
4.5
For this test condition, VDDQ always is equal to VCC.
All typical values are at VCC = 2.5 V, TA = 25°C.
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