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參數(shù)資料
| 型號： | SN74AUP1G08DBVRE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 門電路 |
| 英文描述： | AUP/ULP/V SERIES, 2-INPUT AND GATE, PDSO5 |
| 封裝： | GREEN, PLASTIC, SOT-23, 5 PIN |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 1135K |
| 代理商： | SN74AUP1G08DBVRE4 |
AUP
LVC
AUP
LVC
Static-Power Consumption
(
A)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time ns
V
oltage
V
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
Y + A B or Y + A ) B
1
2
4
A
B
Y
SCES502J – NOVEMBER 2003 – REVISED MAY 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This single 2-input positive-AND gate performs the Boolean function
in positive logic.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE
TOP-SIDE
TA
PACKAGE(2)
PART NUMBER
MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G08YFPR
_ _ _HE_
0.23-mm Large Bump – YFP (Pb-free)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G08YZPR
_ _ _HE_
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G08DRYR
HE
–40°C to 85°C
uQFN – DSF
Reel of 5000
SN74AUP1G08DSFR
HE
SOT (SOT-23) – DBV
Reel of 3000
SN74AUP1G08DBVR
H08_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G08DCKR
HE_
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G08DRLR
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
L
H
L
H
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
2
Copyright 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G08
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74AUP1G08DBVRG4 | 功能描述:邏輯門 Lo PWR SNGL 2Input Pos AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74AUP1G08DBVT | 功能描述:邏輯門 Lo PWR SNGL 2Input Pos AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74AUP1G08DBVTE4 | 功能描述:邏輯門 Lo PWR SNGL 2Input Pos AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74AUP1G08DBVTG4 | 功能描述:邏輯門 Lo PWR SNGL 2Input Pos AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74AUP1G08DCKR | 功能描述:邏輯門 LP Single 2-Input Positive-AND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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