參數(shù)資料
型號(hào)： SN74ALVCH16973DLR
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： ALVC/VCX/A SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
封裝： GREEN, PLASTIC, SSOP-48
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 333K
代理商： SN74ALVCH16973DLR
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
SCES435B – APRIL 2003 – REVISED SEPTEMBER 2004
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place
the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the
high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to VCC
through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of
the drivers.
The four independent noninverting buffers perform the Boolean function Y = D and are independent of the state
of DIR, TOE, LE, and LOE.
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
FUNCTION TABLES
INPUTS
OPERATION
TOE
DIR
L
B data to A bus
L
H
A data to B bus
A bus and B bus
H
X
isolation
INPUTS
OUTPUT
Q
LOE
LE
A
L
H
L
H
L
X
Q0
H
X
Z
INPUT
OUTPUT
D
Y
L
H
2
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