參數(shù)資料
型號(hào): SN74ABT8952DW
廠商: Texas Instruments
文件頁(yè)數(shù): 6/31頁(yè)
文件大小: 0K
描述: IC SCAN-TEST-DEV/XCVR 28-SOIC
標(biāo)準(zhǔn)包裝: 20
系列: 74ABT
邏輯類(lèi)型: 掃描測(cè)試設(shè)備,帶寄存總線收發(fā)器
電源電壓: 4.5 V ~ 5.5 V
位數(shù): 8
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 925 (CN2011-ZH PDF)
其它名稱(chēng): 296-4116-5
SN54ABT8952, SN74ABT8952
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS121D – AUGUST 1992 – REVISED JULY 1996
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 4 and 5 illustrate the 16-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
=
A8-I
B8-O
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
Figure 4. 16-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
=
B8-I
A8-O
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
Figure 5. 16-Bit PRPG Configuration (OEAB = 1, OEBA = 0)
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