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參數(shù)資料
| 型號(hào)： | SN54LVTH646JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 229K |
| 代理商： | SN54LVTH646JT |
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH646
SN74LVTH646
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
MHz
tw
Pulse duration, CLK high or low
3.3
ns
t
Setup time,
Data high
1.3
1.6
1.2
1.5
ns
tsu
,
A or B before CLKAB
↑ or CLKBA↑
Data low
1.9
2.6
1.6
2.2
ns
th
Hold time, A or B after CLKAB
↑ or CLKBA↑
1.2
0.8
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 2)
SN54LVTH646
SN74LVTH646
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
fmax
150
MHz
tPLH
CLKBA or
AorB
1
5.3
5.9
1.8
3.1
4.7
5.6
ns
tPHL
CLKAB
A or B
1.5
5
5.9
1.8
3.1
4.7
5.6
ns
tPLH
AorB
BorA
1
4.9
5.6
1.3
2.3
3.5
4.1
ns
tPHL
A or B
B or A
1.2
4.8
5
1.3
2.4
3.5
4.1
ns
tPLH
SBA or SAB
AorB
1
5.3
6.3
1.5
3
4.9
6
ns
tPHL
SBA or SAB
A or B
1.3
5.3
6.3
1.5
3.3
4.9
6
ns
tPZH
OE
AorB
1
5.4
6.7
1.1
3.1
5.2
6.5
ns
tPZL
OE
A or B
1
5.6
6.7
1.1
3.4
5.2
6.5
ns
tPHZ
OE
AorB
1.7
6.3
6.5
2.3
3.9
5.5
6.1
ns
tPLZ
OE
A or B
2.2
6.3
6.5
2.3
4
5.5
5.9
ns
tPZH
DIR
AorB
1.2
5.6
6.8
1.3
3.4
5.2
6.6
ns
tPZL
DIR
A or B
1.2
6.7
6.8
1.3
3.6
5.2
6.6
ns
tPHZ
DIR
AorB
1.1
7.2
8.1
1.5
3.2
5.6
6.7
ns
tPLZ
DIR
A or B
1.4
6.1
6.6
1.5
3.8
5.6
6.3
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
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