參數(shù)資料
型號(hào)： SN54LVTH18504AHV
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 8/40頁
文件大小： 594K
代理商： SN54LVTH18504AHV
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 5 and 6 show the 40-bit linear-feedback shift-register algorithms through which the
patterns are generated. An initial seed value should be scanned into the BSR before performing this operation.
A seed value of all zeroes does not produce additional patterns.
=
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
B10-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
A8-I/O
A10-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A18-I/O
A20-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B20-I/O
B9-I/O
A9-I/O
A19-I/O
B19-I/O
Figure 5. 40-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
相關(guān)PDF資料
PDF描述
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