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參數(shù)資料
| 型號： | SN54LVTH182512HKC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
| 封裝： | 0.50 MM PITCH, CERAMIC, FP-64 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 518K |
| 代理商： | SN54LVTH182512HKC |
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SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE
universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B
outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar
to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE
universal bus transceivers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of ’LVTH182512, which are designed to source or sink up to 12 mA, include equivalent 25-
series resistors to reduce overshoot and undershoot.
The SN54LVTH18512 and SN54LVTH182512 are characterized for operation over the full military temperature
range of –55
°C to 125°C. The SN74LVTH18512 and SN74LVTH182512 are characterized for operation from
–40
°C to 85°C.
FUNCTION TABLE
(normal mode, each register)
INPUTS
OUTPUT
OEAB
LEAB
CLKAB
A
B
L
X
B0
L
↑
LL
L
↑
HH
L
HX
L
HX
H
X
Z
A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
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