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參數(shù)資料
| 型號： | SN54LV273AFK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20 |
| 封裝： | CERAMIC, CC-20 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 200K |
| 代理商： | SN54LV273AFK |
SN74LV273A, Octal D-Type Flip-Flops With Clear
DEVICE STATUS: ACTIVE
l
EPICTM
(Enhanced-Performance Implanted CMOS) Process
l
Typical V
OLP
(Output Ground Bounce) <0.8 V at V
CC
= 3.3 V, T
A
= 25°C
l
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
l
2-V to 5.5-V V
CC
Operation
l Support Mixed-Mode Voltage Operation on All Ports
l
Latch-Up Performance Exceeds 250 mA Per JESD 17
l
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using
Machine Model (C = 200 pF, R = 0)
l
Package Options Include Plastic Small-Outline (DW, NS), Shrink Small-Outline (DB), Thin
Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat
(W) Packages, Chip Carriers (FK), and DIPs (J)
EPIC is a trademark of Texas Instruments.
The 'LV273A devices are octal D-type flip-flops designed for 2-V to 5.5-V V
CC
operation.
These devices are positive-edge-triggered flip-flops with direct clear (CLR\) input. Information
at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on
the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When the clock
(CLK) input is at either the high or low level, the D-input signal has no effect at the output.
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PRODUCT SUPPORT: TRAINING
PARAMETER NAME SN74LV273A
Voltage Nodes (V) 5, 3.3, 2.5
FEATURES
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DESCRIPTION
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