參數(shù)資料
型號: SN54LS165
廠商: Motorola, Inc.
英文描述: 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER
中文描述: 8位并行到串行移位寄存器
文件頁數(shù): 3/6頁
文件大?。?/td> 207K
代理商: SN54LS165
5-292
FAST AND LS TTL DATA
SN54/74LS165
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
or VIL per Truth Table
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
IIH
Input HIGH Current
Other Inputs
PL Input
20
60
μ
A
VCC = MAX, VIN = 2.7 V
Other Inputs
PL Input
0.1
0.3
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Other Inputs
PL Input
–0.4
–1.2
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Short Circuit Current (Note 1)
–20
–100
mA
VCC = MAX
VCC = MAX
Power Supply Current
36
mA
AC CHARACTERISTICS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
tPLH
tPHL
Maximum Input Clock Frequency
25
35
MHz
CL = 15 pF
Propagation Delay
PL to Output
22
22
35
35
ns
VCC = 5.0 V
tPLH
tPHL
Propagation Delay
Clock to Output
27
28
40
40
ns
tPLH
tPHL
Propagation Delay
P7 to Q7
14
21
25
30
ns
tPLH
tPHL
Propagation Delay
P7 to Q7
21
16
30
25
ns
相關PDF資料
PDF描述
SN54LS166 8-BIT SHIFT REGISTERS
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