參數(shù)資料
型號: SN54LS165
廠商: Motorola, Inc.
英文描述: 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER
中文描述: 8位并行到串行移位寄存器
文件頁數(shù): 2/6頁
文件大小: 207K
代理商: SN54LS165
5-291
FAST AND LS TTL DATA
SN54/74LS165
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The SN54/74LS165 contains eight clocked master/slave
RS flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended set-
up and hold times are observed.
For clock operation, PL must be HIGH. The two clock inputs
perform identically; one can be used as a clock inhibit by
applying a HIGH signal. To avoid double clocking, however,
the inhibit signal should only go HIGH while the clock is HIGH.
Otherwise, the rising inhibit signal will cause the same
response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data can
change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°
C
IOH
IOL
Output Current — High
54, 74
–0.4
mA
Output Current — Low
54
74
4.0
8.0
mA
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