參數(shù)資料
型號(hào)： SN54AS885JT
廠商： TEXAS INSTRUMENTS INC
元件分類： 算術(shù)邏輯單元
英文描述： AS SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, CDIP24
封裝： 0.300 INCH, CERAMIC, DIP-24
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 573K
代理商： SN54AS885JT
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 ,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
SN54AS885
SN74AS885
MIN
TYP
MAX
MIN
TYP
MAX
tPLH
L/A
P < QOUT,
2
8.5
14
1
8.5
13
ns
tPHL
L/A
Q,
P > QOUT
2
7.5
14
1
7.5
13
ns
tPLH
P < QIN,
P < QOUT,
2
5
10
1
5
8
ns
tPHL
,
P > QIN
Q,
P > QOUT
2
5.5
10
1
5.5
8
ns
tPLH
Any P or Q
P < QOUT,
2
13.5
21
1
13.5
17.5
ns
tPHL
y
data input
Q,
P > QOUT
2
10
17
1
10
15
ns
All typical values are at VCC = 5 V, TA = 25°C.
APPLICATION INFORMATION
The
′AS885 can be cascaded to compare words longer than eight bits. Figure 1 shows the comparison of two 32-bit
words; however, the design is expandable to n bits. Figure 1 shows the optimum cascading arrangement for
comparing words of 32 bits or greater. Typical delay times shown are at VCC = 5 V, TA = 25°C and use the standard
advanced Schottky load of RL = 500 , CL = 50 pF.
Figure 2 shows the fastest cascading arrangement for comparing 16-bit or 24-bit words. Typical delay times shown
are at VCC = 5 V, TA = 25°C and use the standard advanced Schottky load of RL = 500 , CL= 50 pF.
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