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參數(shù)資料
| 型號： | SN54AHC595FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS |
| 中文描述： | 8位移位寄存器3態(tài)輸出寄存器 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 446K |
| 代理商： | SN54AHC595FK |
SCLS373I MAY 1997 REVISED JUNE 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
5
SN54AHC595
MIN
5
SN74AHC595
MIN
5
UNIT
MAX
MAX
MAX
SRCLK high or low
tw
Pulse duration
RCLK high or low
5
5
5
ns
SRCLR low
SER before SRCLK
↑
SRCLK
↑
before RCLK
↑
SRCLR low before RCLK
↑
SRCLR high (inactive) before SRCLK
↑
SER after SRCLK
↑
5
5
5
3
3
3
tsu
Setup time
5
5
5
ns
5
5
5
2.5
2.5
2.5
th
Hold time
2
2
2
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
LOAD
TA = 25
°
C
TYP
120*
SN54AHC595
MIN
70*
SN74AHC595
MIN
70
UNIT
(OUTPUT)
CAPACITANCE
MIN
80*
MAX
MAX
MAX
fmax
CL = 15 pF
CL = 50 pF
MHz
55
105
50
50
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
RCLK
QAQH
CL = 15 pF
6*
11.9*
1*
13.5*
1
13.5
ns
6*
11.9*
1*
13.5*
1
13.5
SRCLK
QH
′
CL = 15 pF
6.6*
13*
1*
15*
1
15
ns
6.6*
13*
1*
15*
1
15
SRCLR
QH
′
CL = 15 pF
6.2*
12.8*
1*
13.7*
1
13.7
ns
OE
QAQH
CL = 15 pF
6*
11.5*
1*
13.5*
1
13.5
ns
7.8*
11.5*
1*
13.5*
1
13.5
RCLK
QAQH
CL = 50 pF
7.9
15.4
1
17
1
17
ns
7.9
15.4
1
17
1
17
SRCLK
QH
′
CL = 50 pF
9.2
16.5
1
18.5
1
18.5
ns
9.2
16.5
1
18.5
1
18.5
SRCLR
QH
′
CL = 50 pF
9
16.3
1
17.2
1
17.2
ns
OE
QAQH
CL = 50 pF
7.8
15
1
17
1
17
ns
9.6
15
1
17
1
17
OE
QAQH
CL = 50 pF
8.1
9.3
15.7
15.7
1
1
16.2
16.2
1
1
16.2
16.2
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
2
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