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參數資料
| 型號： | SN54AHC125FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 中文描述： | 翻兩番總線緩沖器門，三態(tài)輸出 |
| 文件頁數： | 1/19頁 |
| 文件大?。?/td> | 650K |
| 代理商： | SN54AHC125FK |
SN54AHC125, SN74AHC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS256J – DECEMBER 1995 – REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN54AHC125 . . . J OR W PACKAGE
SN74AHC125 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN54AHC125 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1
1
N
3
3
V
4
2
G
N
NC – No internal connection
SN74AHC125 . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1
3
V
G
description/ordering information
The ’AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN – RGY
PDIP – N
Tape and reel
Tube
SN74AHC125RGYR
SN74AHC125N
HA125
SN74AHC125N
SOIC – D
Tube
SN74AHC125D
AHC125
Tape and reel
SN74AHC125DR
–40
°
C to 85
°
C
SOP – NS
Tape and reel
SN74AHC125NSR
AHC125
SSOP – DB
Tape and reel
SN74AHC125DBR
HA125
TSSOP – PW
Tube
SN74AHC125PW
HA125
Tape and reel
SN74AHC125PWR
TVSOP – DGV
Tape and reel
SN74AHC125DGVR
HA125
CDIP – J
Tube
SNJ54AHC125J
SNJ54AHC125J
–55
°
C to 125
°
C
CFP – W
Tube
SNJ54AHC125W
SNJ54AHC125W
LCCC – FK
Tube
SNJ54AHC125FK
SNJ54AHC125FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關PDF資料 |
PDF描述 |
|---|---|
| SN74AHC125DGV | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 820pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Sn60 Coated; Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
| SN74AHC125DB | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC125J | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC125W | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC132 | QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN54AHC125J | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC125W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC126 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC126_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| SN54AHC126_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
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