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參數(shù)資料
| 型號： | SN54AH573 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 中文描述： | 有三態(tài)輸出的8個透明D型鎖存器 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 549K |
| 代理商： | SN54AH573 |
SCLS242K OCTOBER 1995 REVISED JANUARY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Operating Range 2-V to 5.5-V V
CC
3-State Outputs Directly Drive Bus Lines
Latch-Up Performance Exceeds 250 mA Per
JESD 17
description/ordering information
The ’AHC573 devices are octal transparent
D-type latches designed for 2-V to 5.5-V V
CC
operation.
When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is
low, the Q outputs are latched at the logic levels
of the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74AHC573N
SN74AHC573N
SOIC DW
Tube
SN74AHC573DW
AHC573
Tape and reel
SN74AHC573DWR
40
°
C to 85
°
C
SOP NS
Tape and reel
SN74AHC573NSR
AHC573
SSOP DB
Tape and reel
SN74AHC573DBR
HA573
TSSOP PW
Tube
SN74AHC573PW
HA573
Tape and reel
SN74AHC573PWR
TVSOP DGV
Tape and reel
SN74AHC573DGVR
HA573
CDIP J
Tube
SNJ54AHC573J
SNJ54AHC573J
55 C to 125 C
CFP W
Tube
SNJ54AHC573W
SNJ54AHC573W
LCCC FK
Tube
SNJ54AHC573FK
SNJ54AHC573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHC573 . . . J OR W PACKAGE
SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHC573 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
1
8
G
L
V
C
&& $##
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PDF描述 |
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| SN54AHC16245 | 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN54AHC240FK | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
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| SN54AHC240W | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN54AHCT00FK | QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SN54AHC00 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
| SN54AHC00_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
| SN54AHC00_10 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
| SN54AHC00FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
| SN54AHC00J | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
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