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參數(shù)資料
| 型號(hào)： | SN54221W |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 諧振器 |
| 英文描述： | TTL/H/L SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 352K |
| 代理商： | SN54221W |
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Product Folder: SN54LS221, Dual Monostable Multivibrators With Schmitt-trigger Inputs
Keyword
Part Number
PRODUCT SUPPORT: TRAINING
SN54LS221, Dual Monostable Multivibrators With Schmitt-trigger Inputs
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54LS221 SN74LS221
Voltage Nodes (V) 5
5
Vcc range (V)
4.5 to 5.5
4.75 to 5.25
Input Level
TTL
Output Level
TTL
FEATURES
q
Dual Versions of Highly Stable SN54121 and SN74121 One Shots
q
SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots
q
Pinout Is Identical to the SN54123, SN74123, SN54LS123, and SN74LS123
q
Overriding Clear Terminates Output Pulse
q
Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flat Packs (W), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
TYPE
MAXIMUM
OUTPUT
PULSE
LENGTH(s)
SN54221
21
SN74221
28
SN54LS221 49
SN74LS221 70
DESCRIPTION
The '221 and 'LS221 devices are monolithic dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transition-
triggered input and a positive-transition-triggered input, either of which can be used as an inhibit input.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering
from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, is also provided by internal latching
circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses
can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximums shown in the above table by choosing appropriate timing components. With Rext = 2 k and
Cext = 0, an output pulse typically of 30 ns is achieved, which can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and
clearing sequences are shown as a part of the switching characteristics waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing
components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 uF) and more than one decade of timing resistance (2 k to 30 k for
the SN54221, 2 k to 40 k for the SN74221, 2 k to 70 k for the SN54LS221, and 2 k to 100 k for the SN74LS221). Throughout these ranges, pulse width is defined by the relationship: tw(out) =
CextRext In2 0.7 CextRext. In circuits where pulse cutoff is not critical, timing capacitance up to 1000 uF and timing resistance as low as 1.4 k can be used. Also, the range of jitter-free output pulse widths is
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