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參數(shù)資料
| 型號： | SMS47 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Cascade Sequencer and Supervisory Controller |
| 中文描述： | 四可編程精密級聯(lián)序列和監(jiān)督控制器 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 923K |
| 代理商： | SMS47 |
11
2087 1.0 04/11/05
SMS47
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 5. Configuration Register 6 (D3 through D7)
Note 1 - Read Only bit D7 is set to a 0. Read only bits
D4 and D3 are revision control and the value indi-
cates the status code of the device (ie. 01 is status
code 1).
Table 4. Configuration Register 5 (D4 through D7)
Table 3. Configuration Register 5 (D0 through D3)
WATCHDOG TIMER
The delay from V
PTH0
until PUP#1 low is t
PDLY1
. There is
a similar t
PDLYX
delay for V1 to PUP#2 and for V2 to
PUP#3. They are programmed in register 7. Cascading will
always occur as indicated in the flow chart (Figure 7).
The Watchdog Timer will generate a reset if it times out. It
can be cleared by a high-to-low transition on WLDI and
restarted.
If the Watchdog times out RESET# will be driven low until
t
PRTO
at which time it will return high. Refer to Figure 4
which illustrates the action of RESET# with respect to the
Watchdog timer and the WLDI input.
If WLDI is held low the timer will free-run generating a series
of resets.
When the Watchdog times out RESET# will be generated.
When RESET# returns high (after t
PRTO
) the timer is reset
to time zero.
Register 6 is also used to set the programmable reset time-
out period (t
PRTO
) and to select the cascade option.
Cascade Delay Programming
The cascade delays are programmed in register 7. Bit 7 of
register 6 must be set to a 0 in order to enable the cascading
of the PUP# outputs. Cascading will not commence until
V
0
is above its programmed threshold.
Each PUP# (-3, -2 and -1) is delayed according to the states
of its Bit 1 and Bit 0 as indicated in Table 9. Refer to Figures
1 and 5 for the detailed timing relationship of the program-
mable power-on cascading.
Table 6. Configuration Register 6 (D0, D1, D2)
n
o
A
3
D
S
M
V
3
B
2
D
1
D
0
B
S
L
V
0
D
V
2
V
1
s
n
e
a
n
e
o
e
d
n
V
d
e
e
s
1
a
g
n
W
e
g
a
v
v
o
e
e
s
e
h
0
a
g
g
n
W
v
d
n
u
h
r
e
a
t
p
e
0
0
0
0
s
e
a
n
e
o
e
d
V
d
r
n
t
p
n
1
1
1
1
7
D
B
d
S
a
e
y
O
M
R
6
D
5
D
4
D
3
D
1
1
O
T
R
0
O
T
R
d
a
e
y
O
x
R
d
a
e
y
O
x
R
n
o
A
0
0
0
t
O
T
R
P
s
m
5
2
=
0
0
1
x
x
t
O
T
R
P
s
m
0
5
=
0
1
0
x
x
t
O
T
R
P
s
m
0
0
1
=
0
1
1
x
x
t
O
T
R
P
s
m
0
0
2
=
7
D
B
S
M
6
D
5
D
4
B
S
D
L
n
o
A
V
3
0
V
2
0
V
1
0
V
0
0
a
s
e
c
n
1
a
t
g
a
n
a
e
R
y
p
u
s
1
1
1
1
CONFIGURATION REGISTERS (CONTINUED)
2
D
1
D
0
B
S
L
D
W
0
1
0
1
0
1
D
n
F
m
m
m
0
0
6
1
0
2
3
0
4
6
o
A
O
0
4
0
8
2
D
0
0
1
1
1
1
W
1
D
0
1
0
0
1
1
W
0
F
0
0
s
s
s
s
s
m
m
0
0
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