- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384926 > SMS46GR06 (Summit Microelectronics, Inc.) Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | SMS46GR06 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| 中文描述： | 四可編程精密監(jiān)控控制器，獨(dú)立重置和4K位的非易失性內(nèi)存 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | SMS46GR06 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
12
SMS46
2083 1.1 06/04/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 8 - START and STOP Conditions
Table 9. Slave Addresses
START and STOP Conditions
When both the data and clock lines are high the bus is said
to be not busy. A high-to-low transition on the data line,
while the clock is high, is defined as the Start condition.
A low-to-high transition on the data line, while the clock
is high, is defined as the Stop condition. See Figure 8.
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device,
either the Master or the Slave, will release the bus after
transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line low to Acknowledge that it
received the eight bits of data. The Master will leave the
SDA line high (NACK) when it terminates a read function.
The SMS46 will respond with an Acknowledge after recog-
nition of a Start condition and its slave address byte. If both
the device and a write operation are selected the SMS46
will respond with an Acknowledge after the receipt of each
subsequent 8-Bit word. In the READ mode the SMS46
transmits eight bits of data, then releases the SDA line, and
monitors the line for an Acknowledge signal. If an Acknowl-
edge is detected and no Stop condition is generated by the
Master, the SMS46 will continue to transmit data. If a
NACK is detected the SMS46 will terminate further data
transmissions and await a Stop condition before returning
to the standby power mode.
Device Addressing
Following a Start condition the Master must output the
address of the Slave it is accessing. The most significant
four bits of the Slave address are the device type
identifier/address. For the SMS46 the default is 1010
BIN
.
The next two bits are the Bus Address. The next bit (the
7th) is the MSB of the memory address.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to 1 a Read operation is selected;
when set to 0 a Write operation is selected.
WRITE OPERATIONS
The SMS46 allows two types of Write operations: byte
Write and page Write. A byte Write operation writes a
single byte during the nonvolatile write period (t
WR
). The
page Write operation, limited to the memory array, allows
up to 16 bytes in the same page to be written during t
WR
.
Byte Write
After the Slave address is sent (to identify the Slave
device and select either a Read or Write operation), a
second byte is transmitted which contains the low order
8 bit address of any one of the 512 words in the array.
Upon receipt of the word address the SMS46 responds with
an Acknowledge. After receiving the next byte of data it
again responds with an Acknowledge. The Master then
terminates the transfer by generating a Stop condition, at
which time the SMS46 begins the internal Write cycle.
While the internal Write cycle is in progress the SMS46
inputs are disabled and the device will not respond to any
requests from the Master.
Page Write (memory only)
The SMS46 is capable of a 16-byte page Write operation.
It is initiated in the same manner as the byte Write
operation, but instead of terminating the Write cycle after
the first data word the Master can transmit up to 15 more
bytes of data. After the receipt of each byte the SMS46 will
respond with an Acknowledge.
The SMS46 automatically increments the address for
subsequent data words. After the receipt of each word the
low order address bits are internally incremented by one.
2047 Fig10
SCL
SDA In
START
Condition
STOP
Condition
7
D
B
S
M
6
D
5
D
4
D
3
D
2
D
1
D
0
B
D
S
L
s
B
B
x
C
M
r
s
s
e
r
d
d
A
e
p
y
6
T
4
e
S
c
e
S
0
0
0
D
s
u
B
S
x
R
)
y
m
M
W
x
/
R
M
x
o
d
y
m
e
n
1
1
1
0
1
1
1
0
1
r
e
n
g
o
e
a
e
M
I
2
C INTERFACE (CONTINUED)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMS46GR07 | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| SMS46 | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| SMS46GCR00 | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| SMS46GCR01 | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| SMS46GCR02 | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMS46GR07 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| SMS47 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller |
| SMS47GCR00 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller |
| SMS47GCR01 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller |
| SMS47GCR02 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。