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| 型號(hào)： | SMS46GR06 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory |
| 中文描述： | 四可編程精密監(jiān)控控制器，獨(dú)立重置和4K位的非易失性?xún)?nèi)存 |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | SMS46GR06 |
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11
2083 1.1 06/04/04
SMS46
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 8. Memory Operating Characteristics
2047 Table10 4.0
Figure 7 - Memory Operating Characteristics
I
2
C INTERFACE
Note (1): These values are guaranteed by design.
MEMORY OPERATION
Data for the configuration registers and the memory array
are read and written via an industry standard two-wire
interface. The bus was designed for two-way, two-line
serial communication between different integrated cir-
cuits. The two lines are a serial data line (SDA) and a
serial clock line (SCL). The SDA line must be connected
to a positive supply by a pull-up resistor, located some-
where on the bus. See Memory Operating Characteris-
tics: Table 8 and Figure 7.
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMS46 will be a Slave device, since
it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
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