- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄384925 > SMS45GCR04 (Summit Microelectronics, Inc.) Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | SMS45GCR04 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| 中文描述： | 四可編程精密級(jí)聯(lián)序列和監(jiān)督控制器4K的位的非易失性內(nèi)存 |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 993K |
| 代理商： | SMS45GCR04 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
10
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 2. Configuration Register 4
CONFIGURATION REGISTERS
SUPPLY AND MONITOR FUNCTIONS
The V
0
, V
1
, V
2,
and V
3
inputs are internally diode-ORed so
that any one of the four can act as the device supply. The
RESET# output will be guaranteed true so long as one of
the four pins is at or above 1V.
Note
: for performing a memory operation (Read
or Write) and to have the ability to change
configuration register contents at least one sup-
ply input must be above 2.7V.
Read/Write operations require a 0.1μF capacitor from the
VDD_CAP node to GND. For optimum performance
connect capacitors from each of the Vx inputs to GND.
Locate the capacitors as physically close to the SMS45 as
possible.
If cascading is enabled, the designer must insure V
0
is the
primary supply and is the first to become active.
Associated with each input is a comparator with a program-
mable threshold for detection of under-voltage or over-
voltage conditions on any of the four supply inputs. The
threshold can be programmed in 5mV increments any-
where within the range of 0.6V to 1.875V or 15mV incre-
ments within the range of 1.8V to 5.625V. Configuration
registers 0, 1, 2, and 3 adjust the thresholds for V
0
, V
1
, V
2,
and V
3
respectively.
If the value contained in any register is all zeroes, the
corresponding threshold will be 0.6V. If the contents were
low range 05
HEX
the threshold would then be 0.625V [0.6V
+ (5
×
0.005V)]. All four registers are configured as 8-Bit
registers.
Table 1. Configuration Registers 0, 1, 2, and 3
RESET FUNCTION AND THRESHOLD RANGE
The reset output has four programmable sources for
activation. Configuration register 4 is used for selecting the
activation source (D7:4), which can be any combination of
V
0
, V
1
, V
2
and V
3
. A monitor input can be programmed to
activate on either an under-voltage or over-voltage condi-
tion. The low-order four bits of configuration register 5
program these options. The reset threshold voltage range
for V0 to V3 can be set for 5mV increments below 1.875V
(low Range = "0") or for 15mV increments above 1.8V (high
range = "1") using Bits D3:0.
The RESET# output will become active when triggered by
a selected activation source such as an under-voltage
7
D
B
S
M
X
X
X
X
V
3
a
V
condition on V1. When this condition ceases, the RESET#
output will remain active for t
PRTO
(programmable reset
time-out). This reset time-out interval takes priority over
the PUP outputs for use of the timer.
The RESET# output has two hardwired sources for activa-
tion: the MR# input, and the expiration of the Watchdog
timer. RESET# will remain active so long as MR# is low,
and will continue driving the RESET# output for t
PRTO
(programmable reset time out) after MR# returns high. The
MR# input cannot be bypassed or disabled.
Refer to Figures 2, 3 and 4 for a detailed illustration of the
relationships among the affected signals.
The status of the four supplies is available at any time over
the I
2
C bus in the high order configuration bits of register 5
(Table 3). A "1" in a bit location indicates a fault on that
supply.
7
D
B
S
M
6
D
5
D
4
D
3
D
2
D
1
D
0
B
S
D
L
n
o
A
1
1
1
1
1
1
1
1
V
5
2
6
=
t
e
m
t
u
a
d
h
s
e
e
a
R
h
e
e
w
o
R
w
o
L
h
s
e
T
h
g
g
H
L
H
(
)
g
s
)
g
=
n
0
0
0
0
0
0
0
0
V
6
=
t
e
m
t
u
a
d
h
n
a
d
0
0
0
0
0
1
1
0
6
+
V
6
×
V
5
2
6
=
)
V
5
0
0
)
6
D
5
D
4
D
3
D
2
D
1
D
0
B
S
V
0
g
n
D
L
n
o
A
V
2
e
T
S
V
1
d
h
t
e
a
n
E
r
g
g
T
E
S
E
R
e
a
R
s
e
g
e
0
0
0
0
w
n
o
a
g
a
L
R
H
R
e
g
1
1
1
1
h
n
e
g
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMS45GCR05 | Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GCR06 | Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GCR07 | Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GR00 | Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GR01 | Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMS45GCR05 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GCR06 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GCR07 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GR00 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
| SMS45GR01 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。