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參數(shù)資料
| 型號： | SMQ320C32PCMM60 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-BIT, 60 MHz, OTHER DSP, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 26/50頁 |
| 文件大?。?/td> | 674K |
| 代理商： | SMQ320C32PCMM60 |
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing for RESET [Q = tc(CI)] (see Figure 26)
NO
’320C32-50
’320C32-60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
50
tsu(RESET)
Setup time, RESET before CLKIN low
10
Q*
17
Q*
ns
51
td(CLKINH-H1H)
Delay time, CLKIN high to H1 high
2
10
2
10
ns
52
td(CLKINH-H1L)
Delay time, CLKIN high to H1 low
2
10
2
10
ns
53
tsu(RESETH-H1L)
Setup time, RESET high before H1 low and after ten H1 clock
cycles
7
6
ns
54
td(CLKINH-H3L)
Delay time, CLKIN high to H3 low
2
10
2
10
ns
55
td(CLKINH-H3H)
Delay time, CLKIN high to H3 high
2
10
2
10
ns
56
tdis(H1H-D)
Disable time, H1 low to D in the high-impedance state
12*
11*
ns
57
tdis(H3HL-A)
Disable time, H3 low to A in the high-impedance state
9*
ns
58.1
td(H3H-CONTROLH)
Delay time, H3 high to control signals high
8*
7*
ns
58.2
td(H1H-RWH)
Delay time, H1 low to R / W high
8*
7*
ns
59
td(H1H-IACKH)
Delay time, H1 high to IACK high
8*
7*
ns
60
tdis(RESETL-ASYNCH)
Disable time, RESET low to asynchronous reset signals in
the high-impedance state
17*
14*
ns
* This parameter is not production tested.
CLKIN
H1
H3
50
51
54
57
58.1
60
59
53
52
55
RESET
IACK
D§
A§
Control
Signals
Asynchronous
Reset Signals #
56
58.2
R/W
10 H1 Clock Cycles
RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown
occurs; otherwise, an additional delay of one clock cycle can occur.
The R / W output is placed in the high-impedance state during reset and can be provided with a resistive pullup, nominally 18 – 22 k
, if undesirable
spurious writes can occur when these outputs go low.
§ In microprocessor mode (MCBL / MP = 0), reset vector is fetched twice with seven software wait states each. In microcomputer mode
(MCBL / MP = 1), the reset vector is fetched two times, with no software wait states.
Control signals include STRBx and IOSTRB.
# Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx .
Figure 26. RESET Timing
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