參數(shù)資料
型號: SMQ320C32PCMM60
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 24-BIT, 60 MHz, OTHER DSP, PQFP144
封裝: PLASTIC, QFP-144
文件頁數(shù): 16/50頁
文件大?。?/td> 674K
代理商: SMQ320C32PCMM60
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)
NO
’320C32-50
’320C32-60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
11
td(H1L - SL)
Delay time, H1 low to STRBx low
0*
9
0*
7
ns
12
td(H1L - SH)
Delay time, H1 low to STRBx high
0*
9
0*
7
ns
13
td(H1H - RWL)
Delay time, H1 high to R / W low (read)
0*
9
0*
8
ns
14
td(H1L - A)
Delay time, H1 low to A valid
0*
9
0*
7
ns
15
tsu(D)R
Setup time, D valid before H1 low (read)
10
ns
16
th(D)R
Hold time, D after H1 low (read)
0
ns
17
tsu(RDY)
Setup time, RDY before H1 low
19
17
ns
18
th(RDY)
Hold time, RDY after H1 low
0
ns
19
td(H1H - RWH) Delay time, H1 high to R / W high (write)
9
8
ns
20
tv(D)W
Valid time, D after H1 low (write)
14
12
ns
21
th(D)W
Hold time, D after H1 high (write)
0*
ns
22
td(H1H - A)
Delay time, H1 high to A valid on back-to-back write cycles
9
8
ns
* This parameter is not production tested.
16
H3
H1
R/W
A
D
RDY
15
13
11
12
14
18
17
STRBx
STRBx remains low during back-to-back operations.
Figure 16. Memory-Read-Cycle Timing
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