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參數(shù)資料
| 型號： | SMM665BFR9 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer |
| 中文描述： | 六通道有源直流輸出控制器，監(jiān)視器，Marginer和音序器 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 872K |
| 代理商： | SMM665BFR9 |
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SMM665B
Preliminary Information
Summit Microelectronics, Inc
2089 1.1 10/20/04
11
I
2
C 2-WIRE SERIAL INTERFACE AC OPERATING
CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.
See Figure 4 Timing Diagram.
Conditions
100kHz
Typ
400kHz
Typ
Symbol
Description
Min
0
4.7
4.0
Max
100
Min
0
1.3
0.6
Max
400
Units
KHz
f
SCL
t
LOW
t
HIGH
SCL Clock Frequency
Clock Low Period
Clock High Period
μ
s
μ
s
t
BUF
Bus Free Time
Before New Transmission
-
Note
1/
4.7
1.3
μ
s
t
SU:STA
Start Condition Setup
Time
Start Condition Hold Time
Stop Condition Setup Time
4.7
0.6
μ
s
t
HD:STA
t
SU:STO
4.0
4.7
0.6
0.6
μ
s
μ
s
t
AA
Clock Edge to Data Valid
SCL low to valid
SDA (cycle n)
SCL low (cycle n+1)
to SDA change
Note
1/
0.2
3.5
0.2
0.9
μ
s
t
DH
Data Output Hold Time
0.2
0.2
μ
s
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
1000
300
1000
300
ns
ns
ns
ns
ns
Note
1/
250
0
150
0
Noise suppression
Configuration
Registers
100
100
t
WR_CONFIG
Write Cycle Time Config
10
10
ms
t
WR_EE
Write Cycle Time EE
Memory Array
5
5
ms
Note: 1/ - Guaranteed by Design.
t
R
t
F
t
HIGH
t
LOW
t
SU:SDA
t
HD:SDA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
t
DH
t
AA
SCL
SDA
(IN)
SDA
(OUT)
t
WR (For Write Operation Only)
Figure 4 - Basic I
2
C Serial Interface Timing
TIMING DIAGRAMS
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