參數(shù)資料
型號： SMJ320C6203W14
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 浮點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 53/64頁
文件大小： 939K
代理商： SMJ320C6203W14
SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 33)
NO.
’
C6701-14
’
C6701-16
UNIT
MASTER
MIN
SLAVE
MIN
MAX
MAX
4
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
12
2
–
3P
ns
5
Hold time, DR valid after CLKX low
4
5 + 6P
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 33)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MASTER
§
MIN
SLAVE
MIN
MAX
MAX
1
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXH-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high#
T
–
4
T + 4
ns
2
L
–
4
L + 4
ns
3
Delay time, CLKX high to DX valid
–
4
4
3P + 1
5P + 17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
*L
–
2
*L + 3
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
*P + 4
*3P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 1
4P + 13
ns
*This parameter is not tested.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
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