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參數資料
| 型號： | SMJ320C6203W14 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮點數字信號處理器 |
| 文件頁數： | 36/64頁 |
| 文件大?。?/td> | 939K |
| 代理商： | SMJ320C6203W14 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)
NO.
’
C6701-14
MIN
’
C6701-16
MIN
UNIT
MAX
MAX
7
tsu(EDV-SSCLKH)
th(SSCLKH-EDV)
Setup time, read EDx valid before SSCLK high
3.8
3.8
ns
8
Hold time, read EDx valid after SSCLK high
1.5
1.5
ns
switching characteristics for synchronous-burst SRAM cycles
(half-rate SSCLK)
(see Figure 16 and Figure 17)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MIN
MAX
MIN
MAX
1
tosu(CEV-SSCLKH)
toh(SSCLKH-CEV)
tosu(BEV-SSCLKH)
toh(SSCLKH-BEIV)
tosu(EAV-SSCLKH)
toh(SSCLKH-EAIV)
tosu(ADSV-SSCLKH)
toh(SSCLKH-ADSV)
tosu(OEV-SSCLKH)
toh(SSCLKH-OEV)
tosu(EDV-SSCLKH)
toh(SSCLKH-EDIV)
tosu(WEV-SSCLKH)
toh(SSCLKH-WEV)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
Output setup time, CEx valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
2
Output hold time, CEx valid after SSCLK high
0.5P
–
2.3
0.5P
–
2
ns
3
Output setup time, BEx valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
4
Output hold time, BEx invalid after SSCLK high
0.5P
–
2.3
0.5P
–
2
ns
5
Output setup time, EAx valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
6
Output hold time, EAx invalid after SSCLK high
0.5P
–
2.3
0.5P
–
2
ns
9
Output setup time, SSADS valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
10
Output hold time, SSADS valid after SSCLK high
0.5P
–
2.3
0.5P
–
2
ns
11
Output setup time, SSOE valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
12
Output hold time, SSOE valid after SSCLK high
0.5P
–
2.3
0.5P
–
2
ns
13
Output setup time, EDx valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
14
Output hold time, EDx invalid after SSCLK high
0.5P
–
2.3
0.5P
–
2.2
ns
15
Output setup time, SSWE valid before SSCLK high
1.5P
–
5.5
1.5P
–
4.5
ns
16
Output hold time, SSWE valid after SSCLK high
0.5P
–
2.3
0.5P
–
2
ns
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