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參數(shù)資料
| 型號(hào)： | SMH4802 |
| 廠商： | Summit Microelectronics, Inc. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Programmable -48V Hot-Swap Controller with Forced Shut Down |
| 中文描述： | 可編程的- 48V熱插拔控制器強(qiáng)制關(guān)機(jī) |
| 文件頁(yè)數(shù)： | 17/20頁(yè) |
| 文件大?。?/td> | 573K |
| 代理商： | SMH4802 |
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17
2062 2.3 6/19/03
SMH4802
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Register Access
The SMH4802 contains a 2-wire bus interface for register
access as explained in the previous section. This bus is
highly configurable while maintaining the industry stan-
dard protocol. The SMH4802 responds to one of two
selectable Device Type Addresses: 1010
BIN
, generally
assigned to NV-memories, or 1011
BIN
, which is the default
address for the SMH4802. The Device Type Address is
assigned by programming bit 3 of Register 8.
Register accesses are also programmable using bits 2
and 1 of Register 8. Accesses can be denied (no reads
or writes), read only, or read/write (default state).
The SMH4802 has three address pins (A2, A1 and A0)
associated with the 2-wire bus. The SMH4802 can be
configured to respond only to the proper serial data string
of the Device Type Address and specific bus addresses
(Register 8, bit 0 set); or to the Device Type Address and
any bus address (Register 8, bit 0 cleared).
PROGRAMMING INFORMATION (
Continued
)
Master/Slave Protocol
The master/slave protocol defines any device that sends
data onto the bus as a transmitter and any device that
receives data as a receiver. The device controlling data
transmission is called the Master and the controlled
device is called the Slave. The SMH4802 is always a
Slave device since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time, because a change on the data line while SCL is high
is interpreted as either a Start or a Stop condition.
Register Bit Maps
The SMH4802 has eight user programmable, nonvolatile
configuration registers. Although 8-bit data transfers are
used for reading and writing the registers, only the 4 least
significant bits of each register are utilized by the device.
Therefore, in each of the following registers, bits 7 through
4 are left blank. Bits 3 through 0 are used as shown for
each register.
DEFAULT CONFIGURATION REGISTER SETTINGS - SMH4802-169
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2062 Reg Table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMH4803A | Distributed Power Hot Swap Controller |
| SMH4803AS | Distributed Power Hot Swap Controller |
| SMH4804 | -48V Programmable Hot Swap Sequencing Power Controller |
| SMH4812 | Distributed Power Hot-Swap Controller |
| SMH4812G | Distributed Power Hot-Swap Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMH4802_09 | 制造商:SUMMIT 制造商全稱(chēng):SUMMIT 功能描述:Programmable -48V Hot-Swap Controller with Forced Shut Down |
| SMH4803 | 制造商:SUMMIT 制造商全稱(chēng):SUMMIT 功能描述:Distributed Power Hot-Swap Controller |
| SMH4803A | 制造商:SUMMIT 制造商全稱(chēng):SUMMIT 功能描述:Distributed Power Hot Swap Controller |
| SMH4803AEK | 制造商:SUMMIT 制造商全稱(chēng):SUMMIT 功能描述:Distributed Power Hot-Swap Controller |
| SMH4803AEKP | 制造商:SUMMIT 制造商全稱(chēng):SUMMIT 功能描述:Distributed Power Hot-Swap Controller |
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