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參數(shù)資料
| 型號(hào)： | SMH4802 |
| 廠商： | Summit Microelectronics, Inc. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Programmable -48V Hot-Swap Controller with Forced Shut Down |
| 中文描述： | 可編程的- 48V熱插拔控制器強(qiáng)制關(guān)機(jī) |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大小： | 573K |
| 代理商： | SMH4802 |
16
SMH4802
2062 2.3 6/19/03
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
PROGRAMMING INFORMATION (
Continued
)
Figure 16. Sequential Bus Cycles
Figure 14. Read Protocol
Figure 15. Write Protocol
After the word address Acknowledge is received by the
Master it immediately reissues a Start condition followed
by another Slave address field with the R/W bit set to
Read. The SMH4802 responds with an Acknowledge and
then transmits the 8 data bits stored at the addressed
location. At this point, the Master sets the SDA line to
discontinues data transmission and reverts to its standby
power mode.
Sequential Reads
Sequential reads can be initiated as either a current
address read or a random access read. The first word is
transmitted as with the other byte Read modes (current
address byte Read or random address byte Read).
However, the Master now responds with an Acknowl-
edge, indicating that it requires additional data from the
SMH4802.
The SMH4802 continues to output data for each Acknowl-
edge received. The Master sets the SDA line to NACK and
generates a Stop condition. During a sequential Read
operation the internal address counter is automatically
incremented with each Acknowledge signal.
For Read operations all address bits are incremented,
allowing the entire array to be read using a single Read
command. After a count of the last memory address the
address counter rolls over and the memory continues to
output data.
Master
SDA
Slave
S
T
A
R
T
1 0
R
/
W
1 0
A
C
K
x x x R x x x x x x x x
A
C
K
x x
x x
N
A
C
K
S
T
O
P
2062 Fig14
Master
SDA
Slave
S
T
A
R
T
1 0
R
/
W
1 0
A
C
K
x x x W
x x x x x x x x
x x
x x
A
C
K
A
C
K
S
T
O
P
2062 Fig15
S
T
A
R
T
A
C
K
A
2
A
1
A
0
R
/
W
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
Typical Write Operation
Typical Read Operation
Master
SDA
Slave
Master
SDA
Slave
2062 Fig16
DEVICE
IDENTIFIER
BUS
ADDRESS
1 0 1 0
S
T
A
R
T
A
C
K
A
2
A
1
A
0
R
/
W
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
DEVICE
IDENTIFIER
BUS
ADDRESS
1 0 1 0
A
C
K
A
2
A
1
A
0
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
N
A
C
K
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| SMH4803AS | Distributed Power Hot Swap Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMH4802_09 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Programmable -48V Hot-Swap Controller with Forced Shut Down |
| SMH4803 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Distributed Power Hot-Swap Controller |
| SMH4803A | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Distributed Power Hot Swap Controller |
| SMH4803AEK | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Distributed Power Hot-Swap Controller |
| SMH4803AEKP | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Distributed Power Hot-Swap Controller |
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