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參數(shù)資料
| 型號： | SME5434PCI-440 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 440 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 393K |
| 代理商： | SME5434PCI-440 |
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SME5431PCI-360
SME5434PCI-440
Preliminary
360/440MHz CPU; 0.25 to 2 MB L2 cache; UPA64S, 66MHz PCI Interfaces
UltraSPARC IIi CPU Module
September 2001
Sun Microsystems, Inc
SIGNAL DESCRIPTIONS
Clock Interface
Symbol
Type [1]
1. KEY: O – output; I – input; I/O – input or output; PECL – Positive Emitter Coupled Logic
Name and Function
UPA_CLK_POS,
UPA_CLK_NEG
O
PECL
Differential 3.3-V, low-voltage PECL clock supplied to the UPA64S interface
PCI_REF_CLK
I
PCI reference clock; should be 66 MHz. But this can be 33 MHz if a 33 MHz PCI
interface is required
PCI_CLK
I
PCI clock; 66 MHz - doubled internally to 133 MHz for use in internal PCI logic
JTAG/Test Interface
Symbol
Type
Name and Function
TDO
O
3.3-V IEEE 1149 test data output; tri-state signal driven only when the TAP controller is
in the shift-DR state
TDI
I
3.3 V IEEE 1149 test data input; pin is internally pulled to logic one when not driven
TCK
I
3.3 V IEEE 1149 test clock
input; pin must always be driven to logical 1 or logical 0 if not tied to a clock source
TMS
I
3.3 V IEEE 1149 test mode select input; internally pulled to logic one when not driven
TRST_L
I
3.3 V IEEE 1149 test reset input (active low); internally pulled to logical one when not
driven
TEMP_SENSE[1:0]
O
Temperature sensing thermistor terminals on the module
MFG_L
I
For manufacturing test use
Initialization Interface
Symbol
Type
Name and Function
PO_RST_L
I
For non power-on resets; for debug; asynchronous assertion and de-assertion; active
low
S_DATA
I
Serial frequency-setting data for the clock synthesizer (part #MC12430)
S_CLK
I
Data clock for module clock synthesizer
S_LOAD
I
Serial load mode pin for clock synthesizer
X_RESET_L
I
Driven to signal XIR traps; for debug; behaves as a non-maskeable interrupt;
asynchronous assertion and de-assertion; active low
SYS_RESET_L
I
Driven for POR (power-on) resets; asynchronous assertion and de-assertion; active low
PCI_RESET_L
O
Resets PCI subsystem; asynchronous assertion and monotonic deassertion; also used
for UPA64S device reset
PCI_CLKSEL[1:0]
O
Selects PCI clock frequency generated on external system board; see page 12
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