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參數(shù)資料
| 型號： | SMD8406501JA |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Programmable Interval Timer |
| 中文描述： | CMOS可編程間隔定時器 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 142K |
| 代理商： | SMD8406501JA |
4-12
Counter
New counts are loaded and Counters are decremented on
the falling edge of CLK.
The largest possible initial count is 0; this is equivalent to 2
16
for binary counting and 10
4
for BCD counting.
The counter does not stop when it reaches zero. In Modes 0,
1, 4, and 5 the Counter “wraps around” to the highest count,
either FFFF hex for binary counting or 9999 for BCD count-
ing, and continues counting. Modes 2 and 3 are periodic; the
Counter reloads itself with the initial count and continues
counting from there.
FIGURE 15. GATE PIN OPERATIONS SUMMARY
FIGURE 16. MINIMUM AND MAXIMUM INITIAL COUNTS
SIGNAL
STATUS
MODES
0
1
LOW OR
GOING LOW
Disables Counting
-
RISING
-
HIGH
Enables Counting
-
1) Initiates
Counting
2) Resets output
after next clock
Initiates Counting Enables Counting
2
1) Disables
counting
2) Sets output im-
mediately high
1) Disables
counting
2) Sets output im-
mediately high
1) Disables
Counting
-
3
Initiates Counting Enables Counting
4
-
Enables Counting
5
Initiates Counting
-
MODE
MIN COUNT
MAX COUNT
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
5
1
0
NOTE: 0 is equivalent to 2
16
for binary counting and 10
4
for BCD
counting.
82C54
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