參數(shù)資料
型號(hào): SM5M2
廠商: Sharp Corporation
英文描述: 4-Bit Single-Chip Microcomputer(LCD Driver)
中文描述: 4位單片機(jī)(LCD驅(qū)動(dòng)器)
文件頁(yè)數(shù): 3/28頁(yè)
文件大?。?/td> 253K
代理商: SM5M2
SM5M2
- 3 -
P0
0
-P0
3
PIN DESCRIPTION
PIN NAME
I/O
FUNCTION
GND, V
DD
, V
DSP
, V
R
I
Power supply pins. The V
DD
, V
DSP
, V
R
pins apply a positive supply with respect
to the GND.
LSI chip test pins. Cannot be used by the user. Connect T and TOSC to GND.
Connect VOSC to V
DD
.
Input pin with built-in pull-up resistor. Hardware-reset the LSI chip when a Low
level signal is input. Normally, a capacitor is connected between it and GND to
form a power-on reset circuit.
Crystal oscillator pins. Connect a crystal oscillator accross [OSC
IN
-OSC
OUT
] to
form a clock generator circuit.
RC oscillator pins. Connect a resistor across [CK
1
-V
DD
] to form a clock generator
circuit. CK
2
is used to test its clock out.
Voice output pin. Output the contents of a voice ROM.
Melody output pin. Outputs the contents of a melody ROM with standard 12
musical scales (555 to 2 114 Hz) in two octaves.
Pins for the LCD's common signals.
Pins for the LCD's segment signals.
Input pin for external interrupt. The IFA flag is set at the rising edge of INTA.
Output ports. The P0 ports are an output port. The accumulator A
CC
can be
transferred to this port by instruction.
P1 and P2 are I/O pins which can switch to input or output pins in 4/3-bit units
by instruction. They can be used as output pins when configured for a key
matrix. The SM5M2 is forced to hardware-reset when all of P1
0
-P1
3
pins are High
level. (By mask option)
T, TOSC, VOSC
I
RESET
I
OSC
IN
, OSC
OUT
I/O
I
O
F
CK
1
, CK
2
Voice
O
H
0
-H
3
S
0
-S
33
INTA
O
O
I
O
P1
0
-P1
3
, P2
0
-P2
2
I/O
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