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參數(shù)資料
| 型號： | SM6010 |
| 廠商： | Sharp Corporation |
| 英文描述： | 16-Bit Single- Chip Microcomputer |
| 中文描述： | 16位單片機(jī) |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 25K |
| 代理商： | SM6010 |
P
RODUCT
I
NFORMATION
Integrated Circuits
Group
APPLICATIONS:
Pager
PDA
Digital Camera
Theinformation for this document is fromtheMcrocomputer Databook, issuedin March 1997.
Copyright 1998, SharpElectronics Corp Al rights reserved Al tradenames aretheregisteredproperty of ther respectiveowners. Specifications aresubect tochangewthout notice
SMT98028
SM6010 16-Bit Single-
Chip Mcrocomputer
FEATURES
CPU
– General purposeregisters 16-bt × 16
– 62 basic instruction (bt manipulation instructions suitabe
for controling, bt transfer instructions, bt branch instruc-
tions, high speedmultipication anddvision instructions
(16-bts × 16-bts, 16-bts ÷ 16-bts, 32-bts ÷ 16-bts)).
– 10 addressing modes
– 16Mof address space
– An interrupt request starts a high performanceautomatic
data transfer (DTS). Appropriatesettings of interrupts and
registers enabehardwareautomatic data transfer. Various
functions can beoperatedsuccessivey andtheresultant data
can alsobesuccessfully bestored
– Systemclock cycle
0.133 μs MN (V
DD
= 4.5 V to5.5 V at 30 MHz main
clock cycle)
0.2 μs MN (V
DD
= 2.7 V to5.5 V at 20 MHz main
clock cycle)
– Seectabesystemclocks dvidedby 2 upto16 main clocks
for lowpower operation
Memory interface
– 16-bt external address bus
– Optional A24 toA16 capabeof 32Mfor data and16Mfor code
Built-in main clock oscillator for systemclock
Built-in subclock oscillator for real timeclock
21 total softwareinterrupts
– 16 maskabeinterrupts (8 external, 8 internal)
– 5 nonmaskabeinterrupts
– Nonmaskabeinterrupts, when usedin conjunction wth
BST instruction, can trigger thesoftwarereset.
Standby function: Halt mode/Stopmode
I/Oports × 40
– Inputs ports × 8 (alsoserveas A/D input)
– I/Oports × 32 (alsoserveas functional pns)
LCD controler
– Framebuffer resides in systemmemory
– LCD dspay modes
1 bt/pxe bnary mode
Gray mode 4-leve 2-bts/pxe and16-leve 4-bts/pxe
LCD dspay data, 4, 2, 1-bt transfer
Maximumresoution
– Horizontal
1,024 pxes in bnary mode
512 pxes in 4-leve gray shademode
256 pxes in 16-leve gray shademode
– Vertical: 256 lines
Support vertical dspay screen
DMA Main memory
→
LCDC buffer
Real timeclock
– Using 32.768 kHz clock
– Seconds, mnutes, hours, days
– 1-mnuteor 1-secondor 1-day interrupt
– Aarmregister
Watchdog timer (overrun detect timer)
– 8-bt × 1
– 51 μs upto209 ms at 10 MHz (internal)
Serial interface Serial interface× 1 channe
SCI (Serial Communication Interface)
– Programmabebetween UART andsynchronized
– UART
Only TxD RxD supported
Built-in baudrategenerator
Stopbt: 1, 2-bt
Even, oddandnon-parity bts
Error detection frame parity overrun
– Synchronized
8-bt data
Error detection: Overrun
SIR (Serial Infra-RedInterface)
– Using UART
– IrDASIR (version 1.0) compatibe
– SharpDASK SIR compatibe
– From2.4 kb/s upto115.2 kb/s IrDAdata rate
– From2.4 kb/s upto57.6 kb/s DASK data rate
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