參數(shù)資料
型號: SM5K3
廠商: Sharp Corporation
英文描述: 4-Bit Single-Chip Microcomputers(Controllers With 10-Bit A/D Converter)
中文描述: 4位單片機(jī)(控制器位A / D轉(zhuǎn)換器10)
文件頁數(shù): 17/28頁
文件大?。?/td> 233K
代理商: SM5K3
SM5K3/SM5K4/SM5K5
- 17 -
IME flag (master enable flag)
The IME enables or disables all interrupts at the
same time. The IE command, when executed, sets
the IME flag and enables the interrupt specified by
the mask flag setting. The ID command resets the
IME flag, disabling process of any interrupt request.
Setting the IME flag to reset after releasing
hardware reset, all interrupts are inhibited.
Mode register RE (interrupt mask flag)
The mode register RE (RE0, RE1 and RE2;
interrupt mask flag) individually enables or disables
three type of interrupts.
Timer/Counter
The SM5K3/5K4/5K5 have a pair of built-in
timer/counter. The timer/counter are used to handle
periodic interrupts and to count. The overflowing
timer can be used to disable the halt mode. The
timer/counter serve as interval timer.
The timer/counter consists of an 8-bit count register
RA, modulo register RB (for counter initial value
setting), 15-bit divider and 4-bit mode register RC
(for count clock selection). The configuration of the
timer/counter is shown in Fig. 10.
f
SYS
System clock
P1
1
pin
( external event clock )
Divider
Mode register
( RC register )
f
SYS
/ 2
0
0
3
3
0
3
0
3 0
3
4
7
4
7
0
3
15
f
SYS
/ 2
7
A
X
A
X
I FT
Modulo register
( RB register )
Count register
( RA register )
After setting B
L
=
0B
H
OUT command ( RB
[ X, A ] )
IN command ( [ X, A ]
RB )
After setting B
L
= 0A
H
OUT command
After setting B
L
= 0A
H
IN command
Interrupt request flag
C
Fig. 10 Configuration of Timer/Counter
Selecting count clock
A count clock is selected by the bit settings in the
mode register RC.
LOWER 2-BIT OF RC BITS
1
SELECTED COUNT CLOCK
0
0
1
1
f
SYS
(system clock)
f
SYS
/2
7
f
SYS
/2
15
External event clock (P1
1
)
0
0
1
0
1
Table 5 Count Clock Selection
相關(guān)PDF資料
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參數(shù)描述
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