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參數(shù)資料
| 型號： | SM320C6701S16 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 58/64頁 |
| 文件大?。?/td> | 939K |
| 代理商： | SM320C6701S16 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
58
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1
(see Figure 36)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MASTER
§
MIN
SLAVE
MIN
MAX
MAX
1
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low#
H
–
4
H + 4
ns
2
T
–
4
T + 4
ns
3
Delay time, CLKX high to DX valid
–
4
4
3P + 1
5P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
*
–
2
*4
*3P + 4
*5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
*L
–
2
*L + 3
2P + 1
4P + 13
ns
*This parameter is not tested.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
7
6
2
1
CLKX
FSX
DX
DR
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SM320C6701W14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701W16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701ZMBW14 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating Point Dig Signal Proc Military RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| SM320C6711B-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGTAL SIGNAL PROCESSORS |
| SM320C6711C-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGTAL SIGNAL PROCESSORS |
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