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參數(shù)資料
| 型號： | SM320C2550GBM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 50 MHz, OTHER DSP, CPGA68 |
| 封裝： | CERAMIC, MO-067AA, MO-066AA, PGA-68 |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 681K |
| 代理商： | SM320C2550GBM |
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SMJ320C25, SMJ320C2550
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the following table.
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
SMJ320C25-50
SMJ320C25
UNIT
PARAMETER
MIN
MAX
MIN
NOM
MAX
UNIT
tc(C)
Cycle time, CLKOUT1/CLKOUT2
80
600
100
600
ns
td(CIH–C)
Delay time, CLKIN high to CLKOUT1/CLKOUT2/STRB high/low
5
28
5
30
(1S
t
Delay time, CLKOUT1 high to CLKOUT2 low,
Q
6
Q3
Q
6
Q
Q6
ns
td(C1–C2)
Delay time, CLKOUT2 high to CLKOUT1 high, etc.
Q – 6
Q + 3
Q – 6
Q
Q + 6
ns
tf(C)
Fall time, CLKOUT1/CLKOUT2/STRB
5
ns
tr(C)
Rise time, CLKOUT1/CLKOUT2/STRB
3
5
ns
tw(CL)
Pulse duration, CLKOUT1/CLKOUT2 low
2Q – 7
2Q + 5
2Q – 8
2Q
2Q + 8
ns
tw(CH)
Pulse duration, CLKOUT1/CLKOUT2 high
2Q – 5
2Q + 7
2Q – 8
2Q
2Q + 8
ns
.This parameter is not production tested
NOTE 1: Q = 1/4tc(C)
timing requirements over recommended operating conditions (see Note 1 )
SMJ320C25-50
SMJ320C25
UNIT
MIN
MAX
MIN
MAX
UNIT
tc(CI)
Cycle time, CLKIN
20
150
25
150
ns
tw(CIL)
Pulse duration, CLKIN low, tc(CI) = 25 ns (see Note 2)
8
10
15
ns
tw(CIH)
Pulse duration, CLKIN high, tc(CI) = 25 ns (see Note 2)
8
10
15
ns
tsu(S)
Setup time, SYNC before CLKIN low
4
Q – 4
5
Q – 5
ns
th(S)
Hold time, SYNC from CLKIN low
4
8
ns
NOTES:
1: Q = 1/4tc(C)
2. Rise and fall times, assuming a 40–60% duty cycle, are incorporated within this specification CLKIN rise and fall times must be less
than 5 ns
Figure 3. Test Load Circuit
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