參數(shù)資料
型號(hào)： GS9092A
廠商： Gennum Corporation
英文描述： GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092A GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁(yè)數(shù)： 36/59頁(yè)
文件大小： 614K
代理商： GS9092A
GS9092A Data Sheet
34715 - 0
February 2006
36 of 59
Table 3-4: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 00h
15-10
–
Not Used
–
–
9
ANC_PKT_INS
Ancillary Packet Insertion Enable. When the FIFO is
configured for ancillary data insertion, set HIGH to begin
inserting ancillary data.
NOTE: Setting ANC_PKT_INS LOW will not
automatically disable ancillary data insertion (see
Ancillary Data Insertion on page 29
).
R/W
0
8-7
FIFO_MODE[1:0]
FIFO Mode: These bits control which mode the internal
FIFO is operating in (see
Table 3-2
)
R/W
0
6
H_CONFIG
Horizontal sync timing output configuration. Set LOW for
active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS word. See
Figure 3-8
in
HVF Timing Signal Inputs on page 32
.
R/W
0
5
352M_CALC
SMPTE 352M Calculation. When set LOW, the GS9092A
will automatically generate packet information prior to
insertion. When set HIGH, the user must program the
VIDEO_FORMAT registers with the SMPTE 352M packet
to be inserted.
R/W
–
4
352M_INS
SMPTE 352M Packet Insertion. The IOPROC_EN pin
and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
NOTE: The user should disable Packet Insertion when
serializing SDTI signals.
R/W
–
3
ILLEGAL_REMAP
Illegal code re-mapping. Detection and correction of
illegal code words within the active picture area. The
IOPROC_EN pin and SMPTE_BYPASS pin must also be
set HIGH. Set HIGH to disable.
R/W
0
2
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error insertion. The GS9092A will generate
and insert EDH packets. The IOPROC_EN pin and
SMPTE_BYPASS pin must also be set HIGH. Set HIGH
to disable.
R/W
0
1
ANC_CSUM_INS
Ancillary Data Checksum insertion. The IOPROC_EN pin
and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. Occurs only when
IOPROC_EN pin and SMPTE_BYPASS pin is HIGH. Set
HIGH to disable.
R/W
0
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