參數(shù)資料
型號(hào)： GS9092A
廠商： Gennum Corporation
英文描述： GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述： GS9092A GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁(yè)數(shù)： 45/59頁(yè)
文件大?。?/td> 614K
代理商： GS9092A
GS9092A Data Sheet
34715 - 0
February 2006
45 of 59
3.7.3.4 Ancillary Data Checksum Generation and Insertion
The GS9092A will calculate checksums for all detected ancillary data packets
presented to the device. These calculated checksum values are inserted into the
data stream prior to serialization.
Ancillary data checksum generation and insertion will only take place if the
ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW.
3.7.3.5 TRS Generation and Insertion
The GS9092A can generate and insert 10-bit TRS code words into the data stream
as required. This feature is enabled by setting the TRS_INS bit of the
IOPROC_DISABLE register LOW.
TRS word generation will be performed in accordance with the timing parameters,
which will be locked either to the received TRS ID words or the supplied H, V, and
F timing signals.
3.8 Parallel-to-Serial Conversion
The parallel data output of the internal data processing blocks is fed to the
parallel-to-serial converter. The function of this block is to generate a serial data
stream from the 10-bit parallel data words.
3.9 Serial Digital Data PLL
The input PCLK pin is internally connected to an integrated phase-locked loop.
This PLL is also responsible for generating all internal clock signals required by the
device. An internal VCO provides the transmission clock rate for the GS9092A.
The PLL and VCO each require a +1.8V DC power supply, which is supplied via
the VCO_VDD / VCO_GND and PLL_VDD / PLL_GND pins. A loop filter capacitor
should also be connected between the LF+ and LF- pins. See
Typical Application
Circuit on page 56.
NOTE: For a SMPTE compliant serial output, the jitter on the input PCLK across
the frequency spectrum should not exceed 350ps.
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