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參數(shù)資料
| 型號： | SLX24C164P |
| 廠商： | SIEMENS AG |
| 英文描述： | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode |
| 中文描述： | 16千位2048 × 8位串行CMOS EEPROM的，I2C同步2線巴士，頁面保護模式 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大小： | 361K |
| 代理商： | SLX24C164P |
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SLx 24C164/P
Semiconductor Group
9
1998-07-27
4
After a START condition, the master always transmits a Command Byte CSW or CSR.
After the acknowledge of the EEPROM a Control Byte follows, its content and the
transmitter depend on the previous Command Byte. The description of the Command
and Control Bytes is shown in
table 2
.
Device Addressing and EEPROM Addressing
The device has an internal address counter which points to the current EEPROM
address.
The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data
byte
– during a byte read, thus the address counter points to the following address after
reading a data byte.
Command Byte
Selects one of the 8 addressable devices:
the chip select bits c2,
c1 and c0 (bit positions b6 to b4) are compared to their
corresponding hard wired input pins CS2, CS1 and CS0,
respectively (c1 is the complement of CS1 pin).
Selects operation:
the least significant bit b0 is low for a write
operation (Chip Select Write Command Byte CSW) or set high for a
read operation (Chip Select Read Command Byte CSR).
Contains address information:
in the CSW Command Byte, the
bit positions b3 to b1 are decoded for the three uppermost EEPROM
address bits A10, A9, A8 (in the CSR Command Byte, the bit
positions b3 to b1 are left undefined).
Following CSW (b0 = 0):
contains the eight lower bits of the
EEPROM address (EEA) bit A7 to A0, or an additional command
byte for the handling of the protection bit.
Following CSR (b0 = 1):
contains the data read out, transmitted by
the EEPROM. The EEPROM data are read as long as the master
pulls down SDA after each byte in order to acknowledge the
transfer. The read operation is stopped by the master by releasing
SDA (no acknowledge is applied) followed by a STOP condition.
Control Byte
Table 2
Command and Control Byte for
I
2
C-Bus Addressing of Chip and EEPROM
Definition
b7
b6
b5
b4
b3
b2
CSW
1
c2
c1
c0
A10 A9 A8 0
CSR
1
c2
c1
c0
x
x
EEA
A7 A6 A5 A4 A3
A2 A1 A0 EEPROM address
Function
b1
b0
Chip Select for Write
Chip Select for Read
x
1
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